1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically, to semiconductor memory devices for stably controlling power mode at high frequency, i.e., power-down mode or self-refresh mode and method of controlling power mode thereof.
2. Discussion of Related Art
Power mode includes power-down mode and self-refresh mode. Power-down mode refers to a state where an external clock signal is enabled. Self-refresh mode refers to a state where an external clock signal is disabled. Self-refresh mode can be simply referred to as a state whose power state is deeper than power-down mode. The entry and exit into and from power-down mode and self-refresh mode are indicated by a level of a clock enable signal synchronized to an external clock signal.
FIGS. 1 and 2 are timing diagrams showing the exit from power mode at high frequency in the related art. These drawings show a phenomenon where malfunction is generated upon exit from power mode.
In FIGS. 1 and 2, an X-time refers to a time until an instruction/address receive control signal (CKEZ_CA_EN) turns on or off an input buffer unit (not shown) (for receiving external command signals (COM) such as an address, a row address strobe signal and a chip select). A Y-time refers to a time until the input buffer unit (not shown) is turned on or off and external command signals are synchronized to an internal clock signal (INT_CLK). Furthermore, NO indicates no operation and DSEL indicates delete.
Referring to FIG. 1, at a time point t0 of an external clock signal (CLK), the buffered clock enable signal (CKE_OUT) is enabled to logic high. At a time point t1 of a buffered clock signal (CLK_OUT), the instruction/address receive control signal (CKEZ_CA_EN) shifts from logic high to logic low. At this time, the instruction/address receive control signal (CKEZ_CA_EN) turns on the input buffer unit (not shown) after the X-time. At a time point t2 (dotted line) of the external clock signal (CLK), the external command signal (COM) is received. After the Y-time, buffered command signals (CS/RAS/CAS/WE_OUT) are generated. An internal clock-generating control signal (CKEZ_CLK_EN) is generated by sensing the instruction/address receive control signal (CKEZ_CA_EN) at a low phase of t0 of the buffered clock signal (CLK_OUT). An internal clock signal (INT_CLK) is generated at a high phase of t1 of the buffered clock signal (CLK_OUT). If so, at a time point at which the internal clock signal (INT_CLK) is generated (i.e., before the buffered command signals (CS/RAS/CAS/WE_OUT) are input to a command latch unit (not shown) after the input buffer unit is turned on), invalid command signals (CS2Z/RAS2/CAS2Z/WEZ) are recognized as internal command signals. Thus, an instruction decoder (not shown) outputs an invalid command such as Mode Register Set (MRS), as shown in FIG. 1.
Referring to FIG. 2, in the case where a low phase margin Td of the buffered clock signal (CLK_OUT) t0 is small or almost no in recognizing the instruction/address receive control signal (CKEZ_CA_EN), the internal clock-generating control signal (CKEZ_CLK_EN) shifts to logic low approximately on the middle of a high phase of the buffered clock signal (CLK_OUT) t1. In this case, the internal clock signal (INT_CLK) is generated as an abnormal short pulse (indicated by a circular dotted line in FIG. 2) with its front side being cut. The short pulse of the internal clock signal (INT_CLK) has a close relation with the degree of the low phase margin of the buffered clock signal (CLK_OUT) t0 and a time until the internal clock-generating control signal (CKEZ_CLK_EN) is generated in recognizing the aforementioned instruction/address receive control signal (CKEZ_CA_EN). Such an unstable short pulse has a problem in that it may generate abnormal invalid internal command signals (CS2Z/RAS2/CAS2Z/WEZ) although the buffered command signals (CS/RAS/CAS/WE_OUT) are valid. Furthermore, at the low phase of the external clock signal (CLK) t2, the input buffer unit (not shown) is turned on and the buffered command signals (CS/RAS/CAS/WE_OUT) are cut at a hold line shown in FIG. 2. This results in a short set-up time (Tsetup). As a result, an invalid internal command can be performed.
FIG. 3 is a timing diagram showing the entry into power mode at high frequency in the related art. From FIG. 3, it can be seen that the short pulse of the internal clock signal (INT_CLK) generated upon exit from power mode is also generated upon entry into power mode.